In an LSI with a transistor or the like of a process rule of 90 nm node and thereafter, a standby off-leak current accompanying miniaturization of elements is not negligible. Therefore, it becomes difficult to improve device performance only by simple miniaturization of a gate length of a transistor, and thus a new approach is needed for improving the device performance.
With such an ultra-miniaturized transistor, the dimension of a channel region located right below a gate electrode is very small as compared with conventional transistors. It is known that the mobility of carriers (electrons and holes) running in the channel region is largely affected by stress applied to the channel region in such a case. Accordingly, a large number of attempts have been made to improve the operation speed of a semiconductor device by adjusting such stress.
In general, in a transistor in which a region of its silicon substrate where an impurity is introduced is the channel, the mobility of holes is smaller than that of electrons. Therefore, improvement of the operation speed of a p-channel MOS transistor using holes as carriers is an important task when designing a semiconductor integrated circuit device. Further, in the p-channel MOS transistor, it is known that the mobility of holes improves by applying uniaxial compressive strain to the channel region. Further, it has been pointed out in principle that, in such a p-channel MOS transistor, the larger the compressive strain generated in the channel region, the more the mobility of holes increases (Non-Patent Document 1).
Further, there has been studied a method in which, when forming a p-channel MOS transistor, recesses are formed in a source region and a drain region of a silicon substrate, and SiGe layers are epitaxially grown in the recesses. In this method, it is possible to increase a compressive strain by increasing Ge fraction in the epitaxially-grown SiGe layers.
However, when the Ge fraction is too high, a lattice mismatch between Si constituting the substrate and SiGe becomes too large, thereby generating dislocation in the SiGe layer. Such dislocation not only weakens the effect of the compressive strain induced by the SiGe layer, but also increases a leak current taking the dislocation as a path. As a result of this, the transistor performance is degraded.
In general, dislocation generated in a SiGe layer epitaxially grown on a silicon substrate occurs easier as the Ge fraction is higher or the thickness thereof is larger (Non-Patent Document 2). In theory, the limit of a film thickness over which the dislocation occurs is referred to as a critical film thickness, and for epitaxially growing a SiGe layer in which no dislocation exists, it is desirable that the thickness thereof is controlled to be equal to or smaller than the critical film thickness. However, in order to make the thickness of the SiGe layer equal to or smaller than the critical film thickness, there is a need that a recess is formed to be shallow, which makes it difficult to apply a sufficient compressive strain to the channel region.
Therefore, in a conventional art, in order to assure the normal operation, the Ge fraction is suppressed to be low. Accordingly, the mobility of carriers is suppressed to be lower than a theoretically possible level.    Patent Document 1: Japanese Laid-open Patent Publication No. 2006-186240    Patent Document 2: Japanese Laid-open Patent Publication No. 2006-278776    Patent Document 3: Japanese Laid-open Patent Publication No. 2006-332337    Non-Patent Document 1: K. Mistry, et al., 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 50-51    Non-Patent Document 2: R. People, et al., Appl. Phys. Lett. Vol. 47(3), 1985